Mc9s12xeq512 144pins chip has two SPI2 (PP4-PP7 and PH4-PH7), the problem is that if SPI System Enable Bit for SPI2 is set, the two SPI2 will work at the same time, but we only need one of the four pins act like SPI function. How to solve the prolem pleas

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Mc9s12xeq512 144pins chip has two SPI2 (PP4-PP7 and PH4-PH7), the problem is that if SPI System Enable Bit for SPI2 is set, the two SPI2 will work at the same time, but we only need one of the four pins act like SPI function. How to solve the prolem pleas

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xiangwu
Contributor I

Mc9s12xeq512 144pins chip has two SPI2 (PP4-PP7 and PH4-PH7), the problem is that if SPI System Enable Bit for SPI2 is set, the two SPI2 will work at the same time, but we only need one of the four pins act like SPI function. How to solve the prolem please?

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kef2
Senior Contributor IV

There's only one SPI2. It's routed either to PP4-PP7 or to PH4-PH7. See MODRR register description.

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iggi
NXP Employee
NXP Employee

Edward is correct.

There are three SPI modules on S12XE device in 144-pin LQFP pacakge:

SPI0 at PS4-PS7 (alternative PM2-PM5)

SPI1 at PH0-PH3 (alternative PP0-PP3)

SPI2 at PH4-PH7 (alternative PP4-PP7)

MODRR configures the re-routing of SPI0, SPI1, and SPI2 on alternative ports.

Regards,

iggi

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kef2
Senior Contributor IV

There's only one SPI2. It's routed either to PP4-PP7 or to PH4-PH7. See MODRR register description.