set up CCSRBAR for core 1

[hv]

Hi,

I'm working on a P2041RDB.  I'm using u-boot for booting.  Is it correct that the CCSRBAR space is only mapped for core0?  So if I'm running core1, I would need to map the CCSRBAR space?

Thanks!

[scottwood]

No, that's not correct.  CCSRBAR controls the mapping of CCSR registers into the physical address space.  Physical address mappings are the same for all cores.

What you do need to do separately on each core is map physical addresses to virtual addresses, but there's nothing special about doing so for CCSR.

[hv]

Since I’m using uboot, uboot sets up the mapping for core0. Therefore, I assume that I need to do this for core1 to access beyond the 4K default for the boot page. From everything I’ve read, uboot only does the setup for core0 and not secondary cores. That’s not correct?

[scottwood]

Also, why are you attaching small blank images to your posts?

[hv]

I didn’t realize I was doing that.

[scottwood]

As I mentioned in decode MAS registers, the U-Boot spin table code will create a secondary initial mapped area (SIMA) mapping.  This mapping is much larger than 4K (but it does not include CCSR).  Please read the ePAPR document for information on the handoff from U-Boot to an OS.  What you see in the chip manual is describing what U-Boot sees, not what the OS sees.

The initial mapping area on the boot cpu does not include CCSR either.  The OS should invalidate all entries other than what was used to map the entry point, and create its own mappings.  Do not rely on other mappings that U-Boot may have created.  Those mappings may change.