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About i.MX6q/d/sl cache controller and data aborts

Question asked by Niranjan Dighe on Apr 29, 2015
Latest reply on Apr 30, 2015 by igorpadykov

Hello All,


I am working on a automotive product based on i.MX6q and recently facing an issue where we see kernel error with message "imprecise external abort". I am trying to analyze it and need to know a few things (which are not very clear in the TRM) -


The i.MX6 uses the cache controller PL310 and the reference manual says -


"The cache controller gives support for sending L3 responses using the response lines of the AXI

protocol back to the processor that initiated the transaction. There are several methods to send

external error responses created by the L3.

The AXI protocol does not provide a method for passing back an error response that is not

combined with its original transaction.

The support provided enables the L1 master core to detect all L3 external aborts, as precise

aborts or as imprecise aborts through the interrupt lines."

I need to understand the highlighted line above. I am unable to find any interrupt line that notifies the processor about the aborts. Is it the case that this "interrupt line" refers to the data abort exception rather than a IRQ thereby calling data abort

exception handler instead of IRQ_handler and that this is a SoC/implementation specific thing?

Thanks in advance,

Niranjan Dighe