AnsweredAssumed Answered

T1042 - SGMII with external PHY Marvell 88e1111 ( MDIO line controlled by FPGA)

Question asked by SPERBER VINCENT on Apr 28, 2015

Hi,

Sorry I write a terrible english.

 

I work in the project using XMC  CPU module (XPedite6101 from X-ES) containing a T1042 processor.

We use the SerDes configuration 0x88. With the XMC module there are two RGMII link with BCM5482S PHY, two SGMII phy-less, and one SGMII with marvell 88e1111.

 

I have a problem with the SGMII to Marvell 88e1111. The CPU doesn't not manage the MDIO, this is a Kintex FPGA which drives the MDIO line.

I configured the PHY in SGMII mode, 1000Mbits, with auto-negotiation.

 

I tried some DTS configuration but it doesn't work.

 

Firstly, I want to know if my DTS is configured correctly.

 

Currently the DTS looks like this:

 

   enet0: ethernet@e0000 {
   cell-index = <0>;
   compatible = "fsl,fman-memac";
   reg = <0xe0000 0x1000>;
   fsl,port-handles = <&fman0_rx0 &fman0_tx0>;
   fixed-link = <1 1 1000 0 0>;
   phy-connection-type = "sgmii";
   ptimer-handle = <&ptp_timer0>;
   };

 

   enet1: ethernet@e2000 {
   cell-index = <1>;
   compatible = "fsl,fman-memac";
   reg = <0xe2000 0x1000>;
   fsl,port-handles = <&fman0_rx1 &fman0_tx1>;
   fixed-link = <2 1 1000 0 0>;
   phy-connection-type = "sgmii";
   ptimer-handle = <&ptp_timer0>;
   };

 

   enet2: ethernet@e4000 {
   cell-index = <2>;
   compatible = "fsl,fman-memac";
   reg = <0xe4000 0x1000>;
   fsl,port-handles = <&fman0_rx2 &fman0_tx2>;
   fixed-link = <3 1 1000 0 0>;
   phy-connection-type = "sgmii";
   ptimer-handle = <&ptp_timer0>;
   };

 

   enet3: ethernet@e6000 {
   cell-index = <3>;
   compatible = "fsl,fman-memac";
   reg = <0xe6000 0x1000>;
   fsl,port-handles = <&fman0_rx3 &fman0_tx3>;
   phy-handle = <&phy0>;
   phy-connection-type = "rgmii";
   ptimer-handle = <&ptp_timer0>;
   };

 

   enet4: ethernet@e8000 {
   cell-index = <4>;
   compatible = "fsl,fman-memac";
   reg = <0xe8000 0x1000>;
   fsl,port-handles = <&fman0_rx4 &fman0_tx4>;
   phy-handle = <&phy1>;
   phy-connection-type = "rgmii";
   ptimer-handle = <&ptp_timer0>;
   };

 

   mdio@fc000 {
   #address-cells = <1>;
   #size-cells = <0>;
   compatible = "fsl,fman-memac-mdio";
   reg = <0xfc000 0x1000>;
   interrupts = <100 1 0 0>;

 

   phy0: ethernet-phy@1 {
   reg = <0x1>;
   flags = <0x2>;
   };
   phy1: ethernet-phy@2 {
   reg = <0x2>;
   flags = <0x2>;
   };
  

};

 

Outcomes