I am confused about the configuration of the SuperSpeed USB Controller in the LS1021A.
In the TRM I have (Rev E - 1/2015), on page 2732, it says:
The USB 3.0 module includes the following features:
• Supports eight programmable, bidirectional USB endpoints
With Linux booted on the Tower board I have, the USB driver has the following register Dump for GHWPARAMS3, which is documented on pg. 2782-2783:
GHWPARAMS3 = 0x04108485
DWC_USB3_CACHE_TOTAL_XFER_RESOURCES = 0x08
DWC_USB3_NUM_IN_EPS = 0x04
DWC_USB3_NUM_EPS = 0x08
DWC_USB3_ULPI_CARKIT = 0
DWC_USB3_VENDOR_CTL_INTERFACE = 1
DWC_USB3_HSPHY_DWIDTH = 2
DWC_USB3_FSPHY_INTERFACE = 0
DWC_USB3_HSPHY_INTERFACE = 1
DWC_USB3_SSPHY_INTERFACE = 1
This tends to indicate that the part has 4 bidirectional USB endpoints (or 8 unidirectional endpoints).
Can you clarify this with Freescale? While 4 bidirectional EPs is OK at SuperSpeed with a dedicated (non-class) protocol, it is not enough for the USB-2 (High speed) Class protocol fallback case.
If indeed the device only support 4 bidirectional EPs, an alternative solution for me could be to split the controller for USB3SS and USB2HS - in particular, I already have the USB2HS implementation done on the Zynq. I am not 100% sure that the LS1021 will be happy with that, though. The proposal here is that the SS signals get run to the LS1021A and that the USB2 signals (DP/DN) get run to the Zynq. What I think will happen if this is what we do, is that if the device is plugged into a SS host, the LS1021A will train the link, and the host will connect SS, and the DP/DN lines will never be activated. OTOH, if the host is not SS, then the LS1021A will not train the link, and the host will connect via USB2 to the Zynq (which has enough EPs for our application).
Can you also ask Freescale about that type of split functionality (in particular - see if they think that is doable, or if it will screw something up for SS operation).