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i.MX23 DC-DC clock domain

Question asked by lategoodbye on Apr 26, 2015
Latest reply on May 19, 2015 by igorpadykov

Hi,

 

according to this question https://community.freescale.com/thread/352940 i created a little ASCII art of the i.MX23 DC-DC clock domain accordingly to the diagramm in the RM:

 

https://gist.github.com/lategoodbye/e1f462869bfd94843d20

 

I guess the third parent clock is clk_tv108m_ng because the frequencies for values 0x04, 0x05, 0x06 and 0x07 doesn't fit to ref_pll or ref_xtal.

 

Is it correct?

 

Thanks Stefan

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