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Regarding EIM Interface as 16bit multiplexed async mode.

Question asked by Samuel Park on Apr 23, 2015
Latest reply on Apr 23, 2015 by igorpadykov

Dear,

My customer wants to use EIM interface as 16bit multiplexed async mode.

please refer to the following below.

 

//iomux setup

static iomux_v3_cfg_t mx6solo_bionet_pads[] = {

...

MX6DL_PAD_EIM_DA0__WEIM_WEIM_DA_A_0,

MX6DL_PAD_EIM_DA1__WEIM_WEIM_DA_A_1,

MX6DL_PAD_EIM_DA2__WEIM_WEIM_DA_A_2,

MX6DL_PAD_EIM_DA3__WEIM_WEIM_DA_A_3,

MX6DL_PAD_EIM_DA4__WEIM_WEIM_DA_A_4,

MX6DL_PAD_EIM_DA5__WEIM_WEIM_DA_A_5,

MX6DL_PAD_EIM_DA6__WEIM_WEIM_DA_A_6,

MX6DL_PAD_EIM_DA7__WEIM_WEIM_DA_A_7,

//MX6DL_PAD_EIM_DA8__WEIM_WEIM_DA_A_8,

//MX6DL_PAD_EIM_DA9__WEIM_WEIM_DA_A_9,

//MX6DL_PAD_EIM_DA10__WEIM_WEIM_DA_A_10,

//MX6DL_PAD_EIM_DA11__WEIM_WEIM_DA_A_11,

//MX6DL_PAD_EIM_DA12__WEIM_WEIM_DA_A_12,

//MX6DL_PAD_EIM_DA13__WEIM_WEIM_DA_A_13,

//MX6DL_PAD_EIM_DA14__WEIM_WEIM_DA_A_14,

//MX6DL_PAD_EIM_DA15__WEIM_WEIM_DA_A_15,

MX6DL_PAD_EIM_CS0__WEIM_WEIM_CS_0,

MX6DL_PAD_EIM_LBA__WEIM_WEIM_LBA,

MX6DL_PAD_EIM_OE__WEIM_WEIM_OE,

MX6DL_PAD_EIM_RW__WEIM_WEIM_RW,

...

}

//eim setup

static void mx6sl_setup_weimcs(void)

{

void __iomem *nor_reg = MX6_IO_ADDRESS(WEIM_BASE_ADDR);

void __iomem *ccm_reg = MX6_IO_ADDRESS(CCM_BASE_ADDR);

unsigned int reg;

struct clk *clk;

u32 rate;

 

reg = readl(ccm_reg + 0x80);

reg |= 0x00000C00;

writel(reg, ccm_reg + 0x80);

 

clk = clk_get(NULL, "emi_slow_clk");

if (IS_ERR(clk))

printk(KERN_ERR "emi_slow_clk not found\n");

 

rate = clk_get_rate(clk);

if (rate != 132000000)

printk(KERN_ERR "Warning: emi_slow_clk not set to 132 MHz!"

" WEIM NOR timing may be incorrect!\n");

 

u32 reg;

void __iomem *weim_base, *iomuxc_base, *ccm_reg;

 

weim_base = MX6_IO_ADDRESS(WEIM_BASE_ADDR);

iomuxc_base = MX6_IO_ADDRESS(MX6Q_IOMUXC_BASE_ADDR);

ccm_reg = MX6_IO_ADDRESS(CCM_BASE_ADDR);

 

writel(0x00C10009, weim_base);

writel(0x00001000, weim_base+ 0x4);

writel(0x20224444, weim_base + 0x8);

writel(0x00000000, weim_base + 0xc);

writel(0x20224444, weim_base + 0x10);

writel(0x00000000, weim_base + 0x14);

writel(0x00000000, weim_base + 0x90);

 

reg = readl(iomuxc_base + 0x4);

reg &= ~0x3F;

reg |= 0x09;

writel(reg, (iomuxc_base + 0x4));

}

 

//EIM Register dump

# ./memtool -32 0x21b8000 29

Reading 0x29 count starting at address 0x021B8000

 

0x021B8000: 00C10009 00001000 20224444 00000000

0x021B8010: 20224444 00000000 00010080 00001000

0x021B8020: 00000000 00000000 00000000 00000000

0x021B8030: 00010080 00001000 00000000 00000000

0x021B8040: 00000000 00000000 00010080 00001000

0x021B8050: 00000000 00000000 00000000 00000000

0x021B8060: 00010080 00001000 00000000 00000000

0x021B8070: 00000000 00000000 00010080 00001000

0x021B8080: 00000000 00000000 00000000 00000000

0x021B8090: 00000000 00140000 00002600 00000014

0x021B80A0: 00000000

 

0x021B8000 - 00C10009 

The value above  is the following.

 

MUM [1], SRD [0], SWR [0] - Asynchronous write/read multiplexed

DSZ [001] - 001 16 bit port resides on DATA[15:0]

 

 

When i write a value (0x0003) in the memory(0x0800000a)

 

 

i expect the following status.

 

in the address latch time.

data1 = 1, data0 = 0

in non latch time

data1 = 1, data0 =1

 

but, the checked results follow as below

 

in the address latch time.

data1 = 0, data0 = 1

in non latch time

data1 = 0, data0 = 1

 

please refer to the attached image to see the waveform.

 

//capture image

violet: data 0

Yellow : data 1

Blue : Latch

Green: WE

 

please refer to the attached pdf file for schematic.

Thanks in advance.

Outcomes