About DDR_SEL setting of IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE on i.MX6Solo

[yuuki]

Dear all,

We want to know the DDR_SEL setting of the IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.

For the DDR_SEL of the IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET register, we found the following URL.
https://community.freescale.com/message/360650#360650

According to this, DDR_SEL should be set in "00"

For the DDR_SEL of the IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register, we want to know  whether the same setting is necessary.

Must this DDR_SEL be set in "00", too?

Best Regards,

Yuuki

[andrewdyer]

see also  imx6 DDR_SEL

[igorpadykov · Accepted solution]

Hi Yuuki

DDR_SEL of the IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register

should be set according to description in RM:

10 LPDDR2

11 DDR3

Best regards

igor

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