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About DDR_SEL setting of IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE on i.MX6Solo

Question asked by yuuki on Apr 23, 2015
Latest reply on Apr 24, 2015 by Andrew Dyer

Dear all,

 

We want to know the DDR_SEL setting of the IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.

 

For the DDR_SEL of the IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET register, we found the following URL.
https://community.freescale.com/message/360650#360650

 

According to this, DDR_SEL should be set in "00"


For the DDR_SEL of the IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register, we want to know  whether the same setting is necessary.

 

Must this DDR_SEL be set in "00", too?

 

Best Regards,

Yuuki

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