I see these values in the MAS registers but not sure what they are telling me:
MAS0 = 0x00000001
MAS1 = 0x80000000
MAS2 = 0x291A0000
MAS3 = 0x00000000
You can find the description of the MAS registers in the EREF manual, or in the Power ISA 2.06.
The TLB entry described above is not valid for translation as all permission bits are clear.
Does NV (Next Victim) = 1 indicates that I have a TLB miss?
Sorry but I'm new at this.
No. Taking a TLB error exception indicates you have a TLB miss. When you've taken a TLB miss (or executed tlbsx or tlbre) NV will contain a suggestion for which ESEL to use. Otherwise (including when taking an ISI/DSI exception, which is what you'd get with the TLB entry you showed), NV is undefined.
So I didn’t have a TLB miss but an ISI/DSI exception. Correct?
FYI, I’m trying to set up MMU on core 1 of a P2041RDB by mimicking what u-boot did with core 0. I guess I didn’t do that correctly.
Did I get an ISI/DSI exception because all the permission bits are clear?
“The TLB entry’s permission bits
(TLB[US,SX,UW,SW,UR,SR]) determine whether the operation should succeed. If permission is denied,
execution of the instruction is suppressed and an instruction or data storage interrupt occurs.”
Yes, if you try to access an address whose TLB entry does not have the relevant permission bit set, you'll get an ISI or DSI.
I think I got a DSI based on these values:
I think the instruction that caused the DSI is this:
stw r3, 0(r11)
I saw this in the EREF:
Software can determine if the exception
occurred during a page table translation by examining ESR[PT] (or GESR[PT] <E.HV>).
I can’t tell what the ESR[PT] is telling me.
ESR[PT] indicates the fault was from a bad entry in a hardware page table (i.e. something pointed to by a TLB1 entry with the indirect bit set). That bit is not set, so I'm not sure why you're asking about it. The only bit set in ESR above is ESR[ST], which indicates that the access was a store rather than a load.
I’m working with a P2041RDB. I’m using uboot as a bootloader. Uboot sets up core 0 and holds other cores in spin loop.
Now I want to set up MMU for core 1 before I release it.
Here’s what I do to set up a mapping that maps addr 1:1 for 64M
// MAS0 = 0x10010000 (TLB1 is selected, IPROT = 1 and 1st entry)
//MAS1 = 0xC0000800 (TSIZE = 64MB)
// MAS2 = 0x00000210 (effective page number = 0 and effective address range = 0,
// share enabled is set and the page is set up as write-thru).
// MAS3 = 0x00000015 (SX=1, SW=1, SR=1)
Does that look correct? The code that I have that following this setup doesn’t work properly. So I just want to check and see if my setup was done correctly.
You can't set up the MMU on core 1 before you release it. You can only set up the MMU on cores you're already running on. The U-boot spin table code will create a mapping for core 1 when it is released. See the documentation of SIMA in ePAPR.
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