Need to know more about IPUv3 with respect to i.MX6Q

[ajithpv]

Hi All,

As part of an IPU, GPU and Display related activity, I'm going through the following documents

1. IMX6DQRM.pdf - i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 2, 06/2014
2. FTF-CON-F0119.pdf - A Deep Dive into Image Processing for i.MX6 Application Processors

I'm using i.MX6Q SABRE SDP platform with Linux kernel 3.10.17 Yocto BSP.

With respect to the above documents and platform, please see my REQUIREMENT following by DOUBTS below:

REQUIREMENT:

Basically my intention is to draw couple of lines (say 1000 lines) using GPU2D module only. This lines I have to give to IPU blocks via 7 planes (virtual screen). Finally these planes will combine and shows the result on a single display.

The 7 planes (virtual screen) combination shall done based on the "1x7 plane" feature which supported by the IPUv3 in-built to the i.MX6Q (as mentioned in below snapshot).

Each virtual screen shall have the same pixel number, drawing buffer in color format and the inherent depth as the real screen (final display).The display port will be either set to LVDS or HDMI. The maximum supported display resolution shall be 1366x768. The pixel should be of the format RGB565.

Each drawing plane shall managed by "double buffer" mechanism in order to suppress the tearing effect during drawing process.

DOUBTS:

1. In-order to support the Double buffering, I came to know that, I can use the following command:
   $ export FB_MULTI_BUFFER=2
   Whether the above command will make all the 7 planes (virtual buffers) into double buffering mode? If no, then how to set double buffering for all these 7 planes?
   
2. In-order to achieve the "Example 2: 1x7 planes" (as mentioned in above snapshot), I have selected the following IPU main flows and IDMAC channels (with respect to graphical drawing) from IMX6DQRM.pdf :
   • MEM-->VDIC-->IC(PRP VF)-->MEM , where VideoIn = IDMAC_CH_25/26; OtherIn=14; Output IDMAC = 21.
     I assume this will take 2 graphical planes (in which the line drawing are present) from the IDMAC and combine it in VDIC. The result will pass into IC and it will then again combine it with another plane and give the result back to IDMAC (or DMFC).
     
   • MEM-->DPSYNC(BG/FG), where VideoIn = IDMAC_CH_23; OtherIn = 27; Output IDMAC = None.
     I assume this channel will take the above result from IDMAC and then it combine with another plane (which also have line drawing) and result give into DC-->DI--> Display.
     
     I would like to know whether above channel configurations are correct. Could you please share the settings which required for "Example 2: 1x7 planes" (for drawing task with on-the-fly combine), if this configuration is not correct.
   • For CSI --> VDIC – There is no channel setting mentioned for combining in VDIC, if the input is coming from CSI. Could you please tell me, how I can configure this connection in-order to achieve "Example 2: 1x7 planes"?
   • For DI --> CSI – There is no IDMAC channel setting available for connecting the DI output to the CSI input. Could you please tell me, how I can configure this connection in-order to achieve "Example 2: 1x7 planes"?
3. The reference manual (IMX6DQRM.pdf) given plenty of channel configuration but when I look into the Linux source - "include/linux/ipu-v3.h" - I have seen only a few channels are mentioned. Whether only these channels are supported in the i.MX6Q SabreSDP? How I can add new channels here?
4. There details about the GPU2D core in the IMX6DQRM.pdf is not enough for understanding the GPU core. I would like to know from where I will get the "Register details/ detailed reference manual" for the Vivante GPU2D core which used in i.MX6Q processor?

Looking forward to your reply...

Thank you in advance,

Ajith P V

[jimmychan]

Answer from the expert:

==================

REQUIREMENT:

The draws on attached presentation are only ideas of what i.MX6 (IC) can do. Unfortunately current Linux Kernel doesn't support these applications. About the 1x7 planes, our current hardwares don't support either because it must have a HW connection from a display interface to the CSI port. These use cases weren't tested.

DOUBTS:

1. FB_MULTI_BUFFER is used to sync the GPU draws to the display refresh sync. 7 planes solution is not implemented on current BSP.

2. There is no documentation or validation tests that validate this solution. I can't provide the solution.

3. You can add or modify as needed

4.

G2D api and instruction can be found in the Graphics user´s guide documentation, here is the link for downloading:

https://www.freescale.com/webapp/Download?colCode=L3.10.53_1.1.0_LINUX_DOCS&location=null&fasp=1&Par...

[ajithpv]

Hi jimmychan​,

Thank you very much for your reply. Based on the answers from the Freescale experts, I understood that, current BSP does not support 1x7 planes. But, I would like to get more clarity on the below queries.

• The draws on attached presentation are only ideas of what i.MX6 (IC) can do. Unfortunately current Linux Kernel doesn't support these applications.

        Does it mean, none of the model shows above supporting in the current BSP? If no, Out of "1x7 planes", "2x4 planes" and "4x2 planes", which and all are supporting in the BSP? If yes, then which model currently supporting in the Linux BSP (other than these models)

• About the 1x7 planes, our current hardwares don't support either because it must have a HW connection from a display interface to the CSI port.

        If we connect the display interface "output" to the CSI "input" via an external cable/ hardware(outside the i.MX6 processor), will it work as desired for this configuration? Or, is it something that should implement inside the DI and CSI module itself?

• You can add or modify as needed

       Could you please provide a link or document which describing how to add a new IDMAC channel in the current Linux BSP? It seems like adding a new channel in the current set-up (Linux BSP) is not a straight-away easy DIY thing.

I appreciate your time to have a look at this thread and looking forward to your reply...

Thank you in advance,

Ajith P V

[jimmychan]

Q1] Does it mean, none of the model shows above supporting in the current BSP? If no, Out of "1x7 planes", "2x4 planes" and "4x2 planes", which and all are supporting in the BSP? If yes, then which model currently supporting in the Linux BSP (other than these models)

[A1] Currently, BSP supports only 2x2 planes.

[Q2]  If we connect the display interface "output" to the CSI "input" via an external cable/ hardware(outside the i.MX6 processor), will it work as desired for this configuration? Or, is it something that should implement inside the DI and CSI module itself?

[A2] There is no connection inside i.MX between display interface and CSI. The slide shows an external wired connection. This application was never tested, but should work.

[Q3] Could you please provide a link or document which describing how to add a new IDMAC channel in the current Linux BSP? It seems like adding a new channel in the current set-up (Linux BSP) is not a straight-away easy DIY thing.

[A3] Sorry, we don't have such document. You can have the i.MX Reference Manual and the linux kernel drivers as references.

[ajithpv]

Thank you jimmychan for the answers.

[A1] Currently, BSP supports only 2x2 planes.

Could you please attach a diagram or snapshot of 2x2 planes (for better understanding), if you have? Does it mean IPUv3-0 alone giving 2x2 planes (2 display output and 2 plane inputs) or IPUv3-0 and IPUv3-1 together giving 2x2 planes (one display from IPUv3-0 module and another from IPUv3-1) or in any other configuration?

This is for my better understanding. I know current BSP can support 4 displays but, confuses regarding the model which it supports.

Thank you in advance,
Ajith P V

[jimmychan · Accepted solution]

Here is the reply from the expert:

On current BSP, there are 2 drivers that can make combining:

- Framebuffer driver (/drivers/video/mxc/mxc_ipuv3_fb.c)

It combines 2 framebufers per IPU using Display Processor (/dev/fb0 and /dev/fb1)

Using the second IPU on i.MXQ/D it can combine more 2 framebuffers into another output display.

This process is automatic. Both framebuffers are automaticaly combined in display.

- IPU driver /dev/mxc_ipu (/drivers/mxc/ipu3/*)

Using /dev/mxc_ipu device, you can make combining using IC (Image converter). This combining is restricted to a 1024x1024 pixels image and need to call an IOCTL for each combining operation.

In case you use i.MX6Q/D that has 2 IPUs, you can make it twice at the same time.

[ajithpv]

Thank you very much jimmychan​ for your answers. The answers provided by you and your team are help me to understand the IPU module and its BSP features, in a better way.

Convey my thanks to the expert too.

[ajithpv]

I would like to know, is there any update on the following queries?

[jimmychan]

forwarded to expert again. I think he will answer to you asap. Have a nice day.

[ajithpv]

Any update?