We have a question about i.MX6SDL CCM.
Please see Table 18-3 in IMX6SDLRM Rev.1.
It shows ACLK_EIM_SLOW_CLK_ROOT = 198MHz (default).
However, according to the initial register setting of CCM_CSCMR1, it seems to be a half of AXI clock frequency (blue line in Figure 18-2).
And according to the initial register setting of CCM_CBCDR, AXI frequency is half of a half of PLL2 396MHz.
So we can get ACLK_EIM_SLOW_CLK_ROOT = 99MHz (a quater of PLL2 396MHz).
Which is correct?