Hello Freescale team,
Our customer is using Vybrid device and their production has already started. Recently, they found a problem(DDR initialization is not completed) on some of their system at the field.
Now they are investigating why DDR initialization is not completed, but they have not narrowed down the root cause yet.We need your help what portion we should focus on for further investigation.
First, here is problem they faced.
After the system normally started, we put the device into LP stop 3 mode. And when this device is returned from this low-power-mode to normal-operation-mode, DDR initialization was not finished sometimes. (CKE has never been asserted.) The rate of occurrence of this issue is not 100%. But they can duplicate it around 70% on the specific non-working system.
Usage scenario and other observation
Could you advise us the condition when CKE pin is asserted? According to RM, the condition of asserting CKE pin is,
"Asserted— Activates internal clock signals and device input buffers and output drivers."
How DDR controller recognizes that "internal clock signals and device input buffers and output drivers" are activated?
The status of PLL (locked or not locked) for DDR controller?
IOW, we want to know the possible conditions where CKE pin is never asserted, even though we initialized the register for DDR controller.