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56F82xx I2C0 master bug?

Question asked by Adam Huang on Apr 15, 2015
Latest reply on Apr 20, 2015 by Adam Huang

When using I2C1 module in 56F82xx DSC, there is no issue; If using I2C0 module in 56F82xx DSC as master, with EEPROM 24LC02 connected, DSC can get ACK from EEPROM for this byte transfer by sending Device Address (0xA0); while get NACK from EEPROM for second byte by sending any ROM Address.


code segment:

    usigned char u8ErrStatus;     u8ErrStatus = 0;       I2C0_Start();     u8ErrStatus = I2C0_MasterByteWrite(u8DevAddr);     u8ErrStatus = I2C0_MasterByteWrite(u8MemAddr);  //failed at 9th pulse of clock when sending 2nd byte          I2C0_RepeatStart();     u8ErrStatus = I2C0_MasterByteWrite(u8DevAddr | 0x01);     u8ErrStatus = I2C0_MasterByteRead(u8Data, I2C0_SEND_NACK);       I2C0_Stop();



Appreciated anyone can point out the mistake in above code segment......or, is there any Errata that can explain why I2C1 can but I2C0 can't.