AnsweredAssumed Answered

Master clock in I2S Master mode

Question asked by Jorge Fernandez on Apr 14, 2015
Latest reply on Apr 15, 2015 by Jorge Fernandez

Hi all,

 

We have a custom board with iMX6D with the 3.10.53 linux kernel. We have connected the STA559 audio codec

using AUDMUX 4 for I2S interface and GPIO_0_CLKO as Master clock, like the SabreLite one. The SSI1 is configured

in master mode. When I play a 44.1KHz sound with aplay and I can see the signals in the scope:

 

AUD4_TXC = I2S_SCLK = 2.82240MHz = 44100Hz x 2 Channels x 32 bits is OK

AUD4_TXD = I2S_DIN is the sound data is OK

AUX4_TXFS = I2S_LRCLK clock to channel left and right is OK

GPIO_0_CLKO = SYS_MCLK = 24MHz is NOT OK!

 

I know the GPIO_0_CLKO is linked to the main 24MHz OSC but we need this clock to be something like

576 * fs, 128 * fs, 256 * fs, 384 * fs, 512 * fs, 768 * fs, etc... where fs = 44.1KHz. Is it possible to get, for

example, 11.2896MHz in GPIO_0_CLK0? How???

 

Thanks!

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