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Using PWM to request DMA for next PWM value

Question asked by Dave Danenberg on Apr 14, 2015
Latest reply on Feb 5, 2016 by Joakim Arnsby

The problem…

I don’t have exact values, but with my system’s K10 clock speeds (Core 72m, PWM 750k), when the PWM duty cycle is set below ~80%, the DMA/PWM appears to work correctly. Then somewhere greater than 80%, the FTM’s DMA request does not get serviced in time for its next reload. Based on my observations, it looks like the DMA request for the next PWM value is sent at the falling edge (FTM comparator) of the PWM – and then pending (ie, double buffered) PWM values are reloaded at the rising edge (FTM reload). What I see is if the time between the falling and rising edges is too short, then the PWM’s new value arrival (via DMA) is not in time for the reload. In this case, the new PWM value appears one FTM cycle later.



What I am wondering is if there is a formula that will describe when the FTM’s DMA request must be asserted to guarantee the next PWM value arrives before the FTM reload. Perhaps this (hypothetical) formula is based on Core clock and PWM rate.