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Provisions of the Round trip time from DDR3 read access time of i.MX6

Question asked by Takashi Takahashi on Apr 12, 2015
Latest reply on Apr 13, 2015 by igorpadykov

Dear community.


How much or there are has like a "Round trip time" provisions of read access time of i.MX6, between  output of  theCK from iMX6 to input of DQS from DDR3 memory ?

There are provisions, for example, delays in wiring length iMX6 CK issued must receive 1 / 2 CK during?


If RALAT set to 0, please let me know.