AnsweredAssumed Answered

imx28 + wl18xx - data out edge selection

Question asked by Jerome Baron on Apr 9, 2015

Hi everyone,

 

I'm trying to communicate with a wl1835 module with my imx28 board, using the imx_2.6.35_maintain kernel. I'm using backport 3.10.19.

I'm having some trouble while I write to the device. I have attached a small log of my problem. Basically, I have a timeout on a CMD53.

I have probed the SDIO bus and I know my device does answer to my command.

It looks like the driver isn't interpreting well the answer. In the log file, there's two transaction, one that succeed and one that fails.

I have seen as much as 6 successful transmission, then a timeout. But almost every time, it's always 1 success then a failure.

 

In my SDIO signal analysis, I saw that my card respond on the falling edge of the clock. The data is prepared on the rising and is valid on the falling.

This is confirmed by the datasheet were we can find this sentence:

"(1) To change the data out clock edge from the falling edge (default) to the rising edge, set the configuration bit."


Question:

- Can it be a problem that my card is answering by default on the falling edge?

- Were is that configuration bit? I guess it's somewhere in the wl18xx driver but cannot find the information.


Any answer/information is welcome.


Best regards,

Jerome

Original Attachment has been moved to: freescale_log.txt.zip

Outcomes