I am currently doing a project which tries to partition the memory space and CPC cache of P4080DS. To achieve this goal, I used two approach:
(1) Modify the hypervisor device tree
(2) Configure the LAW registers and Partition Control Registers of P4080DS
There are some questions that I am a bit confused about the memory mapping of P4080DS:
(1) The base address specified by LAW, are they physical address or virtual address?
(2) If the address specified in LAW registers are physical address, how can Partition Control Register decide the allocation of CPC ways to LAW? Because I thought that the connection between DDR and cache is fixed.
(3) When I was editing the hypervisor device tree, I tried to partition the CPC by adding the allocate-cpc-ways property in physical memory node. Here the pma node, are they refers to physical memory area? Is the address of it physical address?
(4) If the address in PMA is physical memory, same as question (2), how does this achieved?