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HDMI Interlaced Mode Timing Issue

Question asked by Jon Chapman on Apr 6, 2015


The patches published at Patch for iMX6 BSP to support interlaced display on HDMI and LCD interface, which added support for HDMI interlaced modes on the iMX6, do not adhere to the timing requirements specified in the CEA-861 specification.

After applying the new version of "patch4" from the thread specified above, there is a timing issue where the VSYNC signal is offset by one pixel clock from where it should be. The CEA-861 specification states that the VSYNC should be perfectly aligned with the HSYNC signal plus or minus zero pixel clocks for field 1. For field 2 the VSYNC should be Htotal/2 pixel clocks from the leading edge of the HSYNC signal plus or minus zero pixel clocks. In both cases the VSYNC is 1 pixel clock too late. Is there a way to correct this offset on the IPU so that this functions according to the CEA spec?

I raised this issue in the original thread (HDMI Interlaced Modes), but that thread no longer appears to be active.

Thank you,