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MPC5200 SDRAM timing clarification

Question asked by Patrick Gillespie on Apr 6, 2015

On the MPC5200 SDRAM timing, standard SDRAM, read timing, the data setup is specified as a max of 0.3ns.  Normalli I see setup time specified as minimums.  Is this an error, or is there any clarification of why this is specified in this way?  Also, since the user manual says that the read data is sampled with a n internally generated, 1/4 cycle delayed clock, does that impact the timing specs in the datasheet which only reference MEMCLK?

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