I am having problems understanding what should be done with VDDA on i.MX535 for low power state.
The referernce manual 9.5 says:
"All the memories' array supply (VDDA/VDDAL1) and VDD_STATE are connected to a
dedicated supply pin on i.MX53 this is done due to the fact that the memories array
supply does not support a voltage lower then 1.08V. So during DVFS the periphery
supply is lowered along with the rest of the chip."
However the recommended value in stop mode given in AN4604 "Interfacing the MC34709 with the i.MX53" is 0.95V
Furthermore the reference manual also says
"The dedicated array supply needs to be lowered to support a
maximal difference between VDDA/VDDAL1 and VDD of
It is not clear what supply is meant by VDD. I presume this refers to the i.MX53 peripheral supply (VCC)?
When VDDA is not supplied by the PMIC but via the i.MX53 internal 1.2V LDO (VDD_DIG_PLL) (as recommended in AN4604) the voltage reduction of the VDDA has to be done by software *before* stop mode is entered and the PMIC reduces VDDC. This means that, for a short time:
VDDA = 0.95
VCC = 1.3
Hence difference = 350mV > 300mV
Also, is it OK to reduce VDDA to 0.95V while the processor is still running?
Unless, VDDA is connected to a dedicated PMIC supply there doesn't seem to be an alternative...