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Shutting down cores on i.MX6D

Question asked by Adam Garrison on Apr 1, 2015
Latest reply on Aug 13, 2015 by scott10

My team and I are looking into the feasibility of shutting down one of the cores on our dual-core i.MX6 processor to reduce current consumption and thermal output.


I’ve been using the i.MX6DQ Reference Manual (Rev 2) as my main source of information. From searching through this document, it is my understanding that the two cores share the same clock (PLL1) and voltage rail (VDD_ARM_IN) and the only way to control their state is through the System Reset Control Register (SRC_SCR register 0x020D8000) shown in section 60.7.1. This register appears to have the ability to reset and enable/disable individual cores, expect for core0 which cannot be disabled. I don’t see anything else in the document related to disabling cores.


The OS we are using has an option to run on one or two cores. I have verified that changing this option in the OS changes the respective bit (bit 22: core1_enable) in the SRC_SCR register. I’ve also noticed little to no change in current when running on one core instead of two. The change in current was on the order of ~50 µA and which could have been caused by other variables in the system. In section 12.3.1, I see that the ‘POWER_DOMAIN_WRAPPER’ defined as ‘Wrappers to support power off of individual cores’ is not selected for the Cortex-A9 configuration. Does this mean that we cannot gate power to individual cores (i.e. cut power to the silicon of the second core)?


Unless I’m missing something, I’m inclined to think that disabling a core does not necessarily correspond to decreased current consumption and thermal output.


The questions my team has are:

  1. Is it possible to reduce current consumption and thermal output by disabling one of the cores in our dual-core i.MX6 processor?
  2. When a core is disabled on the i.MX6, what happens to that core?
    • Is power to the core actually cut? Or is the silicon still powered, but just not executing instructions?
  3. Is enabling and disabling cores strictly done through the SRC_SCR Control Register (0x020D8000)?
    • Or are there other registers and clocks that need to be gated for the second core to be ‘off’.
  4. Have you heard of customers shutting down cores to save power and/or reduce thermal output?
    • If so, do you know of any documentation you could share with us?
  5. Do you have any other recommendations for power savings?
    • Do you know of any CCM clocks that could be gated for significant power savings?
    • I have Freescale’s AN4509 i.MX6 Power Consumption PDF that lists a few ideas for reducing power consumption.


Any input is appreciated!


Thank you,