I have a question about the Coldfire v4 MMU.
In the bit descriptions of the MMUDR register, it states "If a Harvard TLB implementation is used..." Is there a way to use the MMU TLB *without* the Harvard implementation (i.e. *not* have separate 32 data and 32 code entries)? If so, how? The documentation seems to hint at this both in the description for the MMUDR.R bit (the quote above) and MMUDR.X bit: "If separate ITLB and DTLBs are used..." Implying that there is an option to not have separate ITLB and DTLB.
My goal here is to be able to both read and execute a page of instruction memory and use *only* one entry in the table, rather than two TLB entries (one ITLB entry for execute and one DTLB entry for read). Is this possible?