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FTM generate pulse, Unable to modify CnV register

Question asked by arnogir on Mar 25, 2015
Latest reply on Mar 27, 2015 by arnogir

Hello

 

I'm on a K60 and test to generate pulse to drive stepper motor.

 

I have a working code which can generate a pulse of a determined wide and period. (CNTIN; MOD  / CnV; C(n+1)V)

 

Then with the following code I generate a square signal (CNTIN = 0, MOD = 65535, Cnv = 1, Cn+1V = 0x8000)

 SIM->SCGC6 |= SIM_SCGC6_FTM0_MASK; 
 
 FTM0->MODE = FTM_MODE_WPDIS_MASK | FTM_MODE_INIT_MASK ;  /* Set up mode register */
 FTM0->MODE |= FTM_MODE_FTMEN_MASK;  /* FTMEN bit is write protected. Can be written only when WPDIS = 1 */
 
 FTM0->SC = (uint32_t)0x00UL;  /* Clear status and control register */
 
 FTM0->CNTIN= (uint32_t)0x00UL;  /* Clear counter initial register */
 FTM0->MOD = (uint32_t)(DV_PWM_MODULO-1);  /* Set up modulo register */
 
 FTM0->CNT = (uint32_t)0x00UL;  /* Reset counter register */
 
 
 FTM0->CONTROLS[0].CnSC = FTM_CnSC_ELSB_MASK;  
 FTM0->CONTROLS[1].CnSC = FTM_CnSC_CHIE_MASK;  
 FTM0->COMBINE = FTM_COMBINE_COMBINE0_MASK;  
 
 FTM0->CONTROLS[0].CnV= 1;  /* Allow to modify pulse start */ 
 FTM0->CONTROLS[1].CnV = 0x8000;  /* Allow to modify Pulse end */   
 
 PORTC->PCR[1]= PORT_PCR_MUX(4);
 
 FTM0->SC= (uint32_t)(/* //debug AG FTM_SC_TOIE_MASK |*/ FTM_SC_CLKS(1) | FTM_SC_PS(DV_PWM_PRESCALER));  /* Set up status and control register */
 


 

 

To test some possibility, I just configure the CHn+1IE and Flag to generate the interrupt on Falling edge (Cn+1V = FTM Counter)

 


void __attribute__ ((interrupt)) DV_Pwm_FTM0IRQ(void)
 {
 /* Toggle port debug */
 PTC->PTOR |= 0x00000001;
 
 /* Increment Cn+1V */
 FTM0->CONTROLS[1].CnV++;
 
 FTM0->CONTROLS[1].CnSC &= ~FTM_CnSC_CHF_MASK; // clear flag
 }
 


 

But after test, IT occurs because My debug Pin on PTC0  toggle.

But the Cn+1V which is incremented on the Interrupt has no effect on my output signal which should pass from a initial duty cycle of 50% to 100% and then 0%  to 100% etc...

But signal still 50% duty!.

SYNCEN is set to 0,

 

so I don't see why Cn+1V is not impacted?

 

 

 

I read the RM, But I think the Update register should be OK because SYNCEN = 0 & SYNCMODE = 0):

 

Screen1.jpg

 

 

 

Screen2.jpg

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