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i.mx6 DDR3 clock termination

Question asked by mahi on Mar 24, 2015
Latest reply on Mar 24, 2015 by igorpadykov

Hi community,

 

why are the DDR3 clocks on SabreSD (and other i.MX6 boards) terminated with a single 200R resistor?

 

According to http://www.freescale.com/files/training_pdf/VFTF09_AN111.pdf page 43 you should use "proven JEDEC topologies" which propose a termination with 2 resistors and a capacitor to VDD.

 

Additionally the value of 200R confuses myself - the differential impedance of the clock traces should be 100R (according to the HDG) and I thought, the termination should match the line impedance.

 

 

Best regards,

Martin

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