i.mx6 DDR3 clock termination

[mahi]

Hi community,

why are the DDR3 clocks on SabreSD (and other i.MX6 boards) terminated with a single 200R resistor?

According to http://www.freescale.com/files/training_pdf/VFTF09_AN111.pdf page 43 you should use "proven JEDEC topologies" which propose a termination with 2 resistors and a capacitor to VDD.

Additionally the value of 200R confuses myself - the differential impedance of the clock traces should be 100R (according to the HDG) and I thought, the termination should match the line impedance.

Best regards,

Martin

[igorpadykov · Accepted solution]

Hi Martin

you are right, in general one can use 100R termination resistor and

other, based on ibis modelling and results of DDR tests,

choosing best possible option. 200R allows to get smaller power

consumption compared with 100R and proved to work fine on

i.MX6 and other older reference designs.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------