In the reference schematic for QorIQ p2020 processor's GPCM interfaces, the address and data lines are connected in reverse order. For example, when P2020 processor is interfaced with a NOR flash, its A30 line (address bit 30) is connected to A0. Similarly,
A29 <->(is connected to) A1
Also, Data lines D0<-> D15
D2<-> D13, etc...
Can anybody tell the reason behind such connection requirement?..