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Reversed address, data line connection with P2020 QorIQ processor

Question asked by Akila M on Mar 23, 2015
Latest reply on Mar 23, 2015 by lunminliang

In the reference schematic for QorIQ p2020 processor's GPCM interfaces, the address and data lines are connected in reverse order. For example, when P2020 processor is interfaced with a NOR flash, its A30 line (address bit 30) is connected to A0. Similarly,

A29 <->(is connected to) A1

A28<-> A2

A27<-> A3


Also, Data lines D0<-> D15

                        D1<-> D14

                        D2<-> D13, etc...


Can anybody tell the reason behind such connection requirement?..