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About CSI Gated Clock Mode in i.MX6DQ.

Question asked by Keita Nagashima on Mar 23, 2015
Latest reply on Mar 30, 2015 by Keita Nagashima

Dear All,

 

I have a question about Gated Clock Mode in i.MX6DQ.

Refer to attached file.

Is it possible to input data right in Period 1 and Period 2?

Period 1 : 41508 pixclk (=1650pixel x 25line + 258pixel)

Period 2 : 8362 pixclk (=1650pixel x 5line + 112pixel)

 

[Condition]

- pixclk frequency : 74.25MHz

- Total Line count / frame (Blanking Line + Active Line) : 750

- Active Line count / frame (hsync count) : 720

- Total pixclk count / line (Included blanking) : 1650

- Active pixclk count / line : 1280

 

 

Best Regards,

Keita

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