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About MMDC PHY Read DQS Gating Control Register in i.MX6DQ.

Question asked by Keita Nagashima on Mar 23, 2015
Latest reply on Mar 24, 2015 by igorpadykov

Dear All,

 

I have a question about DDR setting register.

My customer would like to use DDR3_x64.

 

Refer to 44.12.46 MMDC PHY Read DQS Gating Control Register 0 (MMDCx_MPDGCTRL0) in MCIMX6DQRM(Rev.2).

There is below description.

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For Channel 0: DDR3_x16, DDR3_x32, DDR3_x64

For Channel 1: DDR3_x64

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Next, refer to "DG_HC_DEL1" bits.

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Read DQS gating half cycles delay for Byte1 (channel 0 register) and Byte5 in 64-bit mode (channel 1 register)

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Last, refer to "DG_CMP_CYC" and "DG_DIS" bit ,etc.

There isn't the description of channel 0 and channel 1.

 

[Question]

How should one set channel 0 and channel 1 to MMDCx_MPDGCTRL0?

I couldn't understand well...

 

Best Regards,

Keita

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