Is there anyway to control the occurrence rate of the IRQ Receive Interrupt where the CRC is NOT valid. Is there some hidden register to control this spurious Receive Interrupt. I see this on the SARD card hardware with the latest SMAC code. I see this same rate of occurrence on other hardware designs even when I put the MC13192 based Hardware into an RF chamber... NO outside 2.4G Band Signals.
This interrupt happens randomly sometimes 2 or 3 times in 5 a second window.