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NAND ECC

Question asked by Takashi Takahashi on Mar 18, 2015
Latest reply on Mar 19, 2015 by igorpadykov

Dear community.

 

Describes on i.MX6DQ RM Figure 29-1. General-Purpose Media Interface Controller Block Diagram, I want to check the flow of processing to write NAND to it with the parity for the ECC.

 

For example, when writing data 4KByte the NAND flash,

Is my understanding of the following is correct?

 

GPMI FIFO continuous data and send the serial data is sent to the BCH, BCH to calculate parity data per 512 Byte parity data back to GPMI FIFO,

512 Byte data and the parity data through GPMI PIN State Machine, written to the NAND FROM.

 

Mistakes for the understanding of the above.

Below is right?

The ECC (parity data) to write the data to NAND, as Figure 17-1. Hardware BCH Accelerator, by sending data directly to the BCH to calculate the parity data, and the data + parity data to GPMI from there send.

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