AnsweredAssumed Answered

How does the arbitration lost process work in the K20 in polled mode?

Question asked by Gerry Kurz on Mar 18, 2015
Latest reply on Mar 23, 2015 by Kan_Li

The K20 reference manual in the features of the I2C module says the following:

 

"Arbitration-lost interrupt with automatic mode switching from master to slave"


My questions are:

1) Does this automatic mode switching occur in any arbitration lost event, even when polling for the arbitration lost flag or only in interrupt mode?

2) If in polling mode, do I have to manually switch to slave receive mode?

 

The reference manual does not give clear information on how this automatic switching works:


44.4.1.6 Arbitration procedure
The I2C bus is a true multimaster bus that allows more than one master to be connected
on it.
If two or more masters try to control the bus at the same time, a clock synchronization
procedure determines the bus clock. The bus clock's low period is equal to the longest
clock low period, and the high period is equal to the shortest one among the masters.
The relative priority of the contending masters is determined by a data arbitration
procedure. A bus master loses arbitration if it transmits logic level 1 while another master
transmits logic level 0. The losing masters immediately switch to slave receive mode and
stop driving SDA output. In this case, the transition from master to slave mode does not
generate a STOP condition. Meanwhile, hardware sets a status bit to indicate the loss of
arbitration.


44.4.6.4 Arbitration lost interrupt
The I2C is a true multimaster bus that allows more than one master to be connected on it.
If two or more masters try to control the bus at the same time, the relative priority of the
contending masters is determined by a data arbitration procedure. The I2C module asserts
the arbitration-lost interrupt when it loses the data arbitration process and the ARBL bit
in the Status Register is set.


Arbitration is lost in the following circumstances:
1. SDA is sampled as low when the master drives high during an address or data
transmit cycle.
2. SDA is sampled as low when the master drives high during the acknowledge bit of a
data receive cycle.
3. A START cycle is attempted when the bus is busy.
4. A repeated START cycle is requested in slave mode.
5. A STOP condition is detected when the master did not request it.
The ARBL bit must be cleared (by software) by writing 1 to it.

Outcomes