Hello All,
Here's the code that generates the pulse on PTE, the output measured on PTE_PTE0 is a square wave with a period of 11us, and the output measured on PTE_PTE1 is 0 at all time.
Regards,
PQ
/*
** ###################################################################
** This code is generated by the Device Initialization Tool.
** It is overwritten during code generation.
** USER MODIFICATION ARE PRESERVED ONLY INSIDE INTERRUPT SERVICE ROUTINES
**
** Project : PeterQian
** Processor : MC68HC908GP32CP
** Version : Bean 01.110, Driver 01.00, CPU db: 2.89.061
** Datasheet : MC68HC908GP32 Rev. 7 03/2006
** Date/Time : 29/10/2007, 11:30 AM
** Abstract :
** This bean "MC68HC908GP32_40" provides initialization of the
** CPU core and shared peripherals.
** Settings :
** Clock setting
** External clock : 9.8304 MHz
** CPU mode selection : 1
** Initialization interrupt priority : 1
** Stop instruction enabled : no
** LVI module : yes
**
** Source clock : Main clock frequency / 1
** Internal bus clock : 2.4576 MHz
** Contents :
** Function "MCU_init" initializes selected peripherals
**
** (c) Copyright UNIS, spol. s r.o. 1997-2006
** UNIS, spol s r.o.
** Jundrovska 33
** 624 00 Brno
** Czech Republic
** http : www.processorexpert.com
** mail : info@processorexpert.com
** ###################################################################
*/
#include <MC68HC908GP32.h> /* I/O map for MC68HC908GP32CP */
#define CGM_DELAY 0x27FFUL
/*
** ===================================================================
** Method : MCU_init (bean MC68HC908GP32_40)
**
** Description :
** Device initialization code for selected peripherals.
** ===================================================================
*/
void MCU_init(void)
{
/*** ### MC68HC908GP32_40 "Cpu" init code ... ***/
/*** PE initialization code after reset ***/
/* System clock initialization */
/* Common initialization of the write once registers */
/* CONFIG1: COPRS=0,LVISTOP=0,LVIRSTD=0,LVIPWRD=0,LVI5OR3=0,SSREC=0,STOP=0,COPD=1 */
CONFIG1 = 0x01;
/* CONFIG2: OSCSTOPENB=0,SCIBDsrc=0 */
CONFIG2 = 0x00;
/* Common initialization of the CPU registers */
/* PTDPUE: PTDPUE5=0,PTDPUE4=0 */
PTDPUE &= (unsigned char)~0x30;
/* ### Init_GPIO init code */
/* PTE: PTE1=0,PTE0=0 */
PTE &= (unsigned char)~0x03;
/* DDRE: DDRE1=1,DDRE0=1 */
DDRE |= (unsigned char)0x03;
/* ### Init_TIM init code */
/* T1SC: TOF=0,TOIE=0,TSTOP=1,TRST=1,PS2=0,PS1=0,PS0=0 */
T1SC = 0x30; /* Stop and reset counter */
T1CH0 = 0x0190; /* Compare 0 value setting */
(void)(T1SC0 == 0); /* Channel 0 int. flag clearing (First part) */
/* T1SC0: CH0F=0,CH0IE=1,MS0B=0,MS0A=1,ELS0B=1,ELS0A=1,TOV0=1,CH0MAX=0 */
T1SC0 = 0x5E; /* Int. flag clearing (2nd part) and channel contr. register setting */
T1CH1 = 0xFA; /* Compare 1 value setting */
(void)(T1SC1 == 0); /* Channel 1 int. flag clearing (First part) */
/* T1SC1: CH1F=0,CH1IE=1,MS1A=1,ELS1B=0,ELS1A=1,TOV1=1,CH1MAX=0 */
T1SC1 = 0x56; /* Int. flag clearing (2nd part) and channel contr. register setting */
T1MOD = 0x0320; /* Period value setting */
(void)(T1SC == 0); /* Overflow int. flag clearing (first part) */
/* T1SC: TOF=0,TOIE=1,TSTOP=0,TRST=0,PS2=0,PS1=1,PS0=0 */
T1SC = 0x42; /* Int. flag clearing (2nd part) and timer contr. register setting */
/* ### */
asm CLI; /* Enable interrupts */
} /*MCU_init*/
/*
** ===================================================================
** Interrupt handler : isrINT_TIM1Ovr
**
** Description :
** User interrupt service routine.
** Parameters : None
** Returns : Nothing
** ===================================================================
*/
__interrupt void isrINT_TIM1Ovr(void)
{
/* Write your interrupt code here ... */
// PTA_PTA3 = ~PTA_PTA3
}
/* end of isrINT_TIM1Ovr */
/*
** ===================================================================
** Interrupt handler : isrINT_TIM1CH1
**
** Description :
** User interrupt service routine.
** Parameters : None
** Returns : Nothing
** ===================================================================
*/
__interrupt void isrINT_TIM1CH1(void)
{
/* Write your interrupt code here ... */
PTE_PTE1 =~PTE_PTE1;
}
/* end of isrINT_TIM1CH1 */
/*
** ===================================================================
** Interrupt handler : isrINT_TIM1CH0
**
** Description :
** User interrupt service routine.
** Parameters : None
** Returns : Nothing
** ===================================================================
*/
__interrupt void isrINT_TIM1CH0(void)
{
/* Write your interrupt code here ... */
PTE_PTE0 =~PTE_PTE0;
}
/* end of isrINT_TIM1CH0 */
/* Initialization of the CPU registers in FLASH */
#define UNASSIGNED_ISR 0xFFFF /* Unassigned interrupt service routine */
extern void _Startup(void); /* reset interrupt service routine */
void (* const _vect[])() @0xFFDC = { // Interrupt vector table
UNASSIGNED_ISR, /* Int.no. 0 INT_TBM (at FFDC) Unassigned */
UNASSIGNED_ISR, /* Int.no. 1 INT_ADC (at FFDE) Unassigned */
UNASSIGNED_ISR, /* Int.no. 2 INT_KBD (at FFE0) Unassigned */
UNASSIGNED_ISR, /* Int.no. 3 INT_SCITransmit (at FFE2) Unassigned */
UNASSIGNED_ISR, /* Int.no. 4 INT_SCIReceive (at FFE4) Unassigned */
UNASSIGNED_ISR, /* Int.no. 5 INT_SCIError (at FFE6) Unassigned */
UNASSIGNED_ISR, /* Int.no. 6 INT_SPITransmit (at FFE8) Unassigned */
UNASSIGNED_ISR, /* Int.no. 7 INT_SPIReceive (at FFEA) Unassigned */
UNASSIGNED_ISR, /* Int.no. 8 INT_TIM2Ovr (at FFEC) Unassigned */
UNASSIGNED_ISR, /* Int.no. 9 INT_TIM2CH1 (at FFEE) Unassigned */
UNASSIGNED_ISR, /* Int.no. 10 INT_TIM2CH0 (at FFF0) Unassigned */
isrINT_TIM1Ovr, /* Int.no. 11 INT_TIM1Ovr (at FFF2) Used */
isrINT_TIM1CH1, /* Int.no. 12 INT_TIM1CH1 (at FFF4) Used */
isrINT_TIM1CH0, /* Int.no. 13 INT_TIM1CH0 (at FFF6) Used */
UNASSIGNED_ISR, /* Int.no. 14 INT_PLL (at FFF8) Unassigned */
UNASSIGNED_ISR, /* Int.no. 15 INT_IRQ (at FFFA) Unassigned */
UNASSIGNED_ISR, /* Int.no. 16 INT_SWI (at FFFC) Unassigned */
_Startup /* Int.no. 17 INT_RESET (at FFFE) Reset vector */
};
/* END */
/*
** ###################################################################
**
** This file was created by UNIS Processor Expert 3.00 [03.89]
** for the Freescale HC08 series of microcontrollers.
**
** ###################################################################
*/
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
This should be fairly automatic in most cases as you would probably read from these anyway. However a trap for you if you don't.