Dear Sir or Madam,
My customer is using EIM in DTACK mode with BCLK=100 MHz.
Refer to attached waveform.
The period of EIM_CSx_B=High (between CS active and CS active) =240 ns both of read/write.
They tuned up the CCM setting and the period shorted from 240 ns to 150 ns.
But, their target is less than 100 ns.
- Board: Custom board
- Software: Assembler code
- Other: No use the SDMA
Could you tell me the way of making short the interval of between CS active (Transfer data) and CS active (Transfer data)?
メッセージ編集者: Keita Nagashima