We designed a custom board based on i.MX53 and LPDDR2. After figuring out the configuration of the SDRAM controller for the LPDDR2, and adjusted the DCD, we tried to boot the board from SD card. The board does not boot.
Debugging under JTAG we found out the following :
1. If the SDRAM controller is initialized through the JTAG, the board does boot.
2. Stepping through the boot ROM, we found out that the DCD is copied from the SD card to the iRAM, but the i.MX53 registers are never initialized according to this DCD table.
3. Debugging further the boot ROM, we found out that 2 compares in the boot ROM code are validated (code snippets below).
4. Strangely, when doing the same debug on another completely different board (still i.MX53 but DDR3) that is working for some time and does boot when used without debugger, presents the same problem at the 2 compares and does not boot when the debugger is used.
Debugger used : Segger JLink Ultra+
Boot ROM code snippets :
40831e: 2200 movs r2, #0
408320: 20dd movs r0, #221 ; 0xdd
408322: 4611 mov r1, r2
408324: f7ff fe11 bl 0x407f4a ;
408328: 28f0 cmp r0, #240 ; 0xf0 <=== Here we have 0x33 = 51 in r0
40832a: d10e bne.n 0x40834a ; TAKEN!!
40d6ca: f7fd ff5b bl 0x40b584 ; @MF this also returns 33...
40d6ce: 28f0 cmp r0, #240 ; 0xf0 <=== Here also we have 0x33 = 51 in r0
40d6d0: d10e bne.n 0x40d6f0 ; Taken when forced earlier...
if we put breakpoints at the 2 compares above and force r0 at 0xF0 = 240, the board boots from SD...
Does anybody know what these two compares achieve or why this setup brings these values of 51 instead of 240 ?
Is there a way to get the source code of the boot ROM to understand why the board does not boot ?
Any hints or help would be appreciated,