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V4L not getting ioctl interrupts from IPU2 of IMX6Q

Question asked by Nathan Mak on Mar 3, 2015
Latest reply on Mar 3, 2015 by Nathan Mak

I'm trying to run CSI1 data into IPU2 from an ADV7180 similar to how the sabre board runs CSI0 data into IPU1 from an ADV7180.

 

The problem

when I run "gst-launch -v tvsrc device=/dev/video1 ! mfw_ipucsc ! videocrop left=40 right=40 ! mfw_v4lsink " is a "ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0"

This is caused because v4l2 isn't getting ioctl interrupts as it should be.

 

For testing purposes I have disabled running both at the same time since I know the default ADV7180 driver can only support one.

 

I suspect either my pin muxing is incorrect, or I have IPU2 incorrectly configured

 

What works

- gst-launch -v tvsrc device=/dev/video0 ! mfw_ipucsc ! videocrop left=40 right=40 ! mfw_v4lsink  successfully outputs video

- an oscilloscope shows that data is being sent over the CSI1 lines and thus the ADV7180 initializes correctly over I2C

 

My current setup

Here are my relevant pin muxes

imx6q.dtsi

/{

&soc

ipu2: ipu@02800000 {

compatible = "fsl,imx6q-ipu";

reg = <0x02800000 0x400000>;

interrupts = <0 8 0x4 0 7 0x4>;

clocks = <&clks 133>, <&clks 134>, <&clks 137>,

<&clks 41>, <&clks 42>,

<&clks 135>, <&clks 136>;

clock-names = "bus", "di0", "di1",

"di0_sel", "di1_sel",

"ldb_di0", "ldb_di1";

resets = <&src 4>;

bypass_reset = <0>;

};

};

};

 

&iomuxc {

  ipu2 {

  pinctrl_ipu2_1: ipu2grp-1 { /* parallel camera */

  fsl,pins = <

  MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12     0x80000000

  MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13     0x80000000

  MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14     0x80000000

  MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15     0x80000000

  MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16     0x80000000

  MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17     0x80000000

  MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18     0x80000000

  MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19     0x80000000

  //MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x80000000

  MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK     0x80000000

  MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC     0x80000000

  MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC     0x80000000

  >;

  };

  };

};

 

custom.dtsi

/{

#if 1

  v4l2_cap_0 {

  compatible = "fsl,imx6q-v4l2-capture";

  ipu_id = <0>;

  csi_id = <0>;

  mclk_source = <0>;

  status = "okay";

  };

#endif

 

#if 1

  v4l2_cap_1 {

  compatible = "fsl,imx6q-v4l2-capture";

  ipu_id = <1>;

  csi_id = <1>;

  mclk_source = <0>;

  status = "okay";

  };

#endif


 

 

#if 1

  v4l2_out {

  compatible = "fsl,mxc_v4l2_output";

  status = "okay";

  };

#endif

};

&i2c3 {

  clock-frequency = <100000>;

  pinctrl-names = "default";

  pinctrl-0 = <&pinctrl_i2c3_3>;

  status = "okay";

 

  #if 1 // Don't activate more than one at a time until ADV7180.c is modified

  adv7180_camera1: adv7180@21 {

  compatible = "adv,adv7180";

  reg = <0x21>; // I2C address is actually 0x42 but bitshifted

  pinctrl-names = "default";

  pinctrl-0 = <&pinctrl_ipu1_2>;

  clocks = <&clks 201>;

  clock-names = "csi_mclk";

  DOVDD-supply = <&reg_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */

  AVDD-supply = <&reg_3p3v>;  /* 1.8v */

  DVDD-supply = <&reg_3p3v>;  /* 1.8v */

  PVDD-supply = <&reg_3p3v>;  /* 1.8v */

  //pwn-gpios = <&gpio4 30 0>;

  csi_id = <0>;

  mclk = <24000000>;

  mclk_source = <0>;

  cvbs = <1>;

  };

  #endif

 

  #if 0 // Don't activate more than one at a time until ADV7180.c is modified

  adv7180_camera2: adv7180@20 {

  compatible = "adv,adv7180";

  reg = <0x20>; // I2C address is actually 0x40 but bitshifted

  pinctrl-names = "default";

  pinctrl-0 = <&pinctrl_ipu2_1>;

  clocks = <&clks 201>;

  clock-names = "csi_mclk";

  DOVDD-supply = <&reg_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */

  AVDD-supply = <&reg_3p3v>;  /* 1.8v */

  DVDD-supply = <&reg_3p3v>;  /* 1.8v */

  PVDD-supply = <&reg_3p3v>;  /* 1.8v */

  //pwn-gpios = <&gpio4 30 0>;

  csi_id = <1>;

  mclk = <24000000>;

  mclk_source = <0>;

  cvbs = <1>;

  };

  #endif

 

 

};

 

Sources that have helped me get this far

https://community.freescale.com/message/435854#435854 - I used portions of Omar's patch to set up CSI0 and CSI1 where by default freescale refers only to CSI0.

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