we're currently using various Kinetis K-Series processors in various projects (K10/22/61/70). Now we have started a project where we need much memory but very low power consumption most of the time.
We wanted to achieve this by using LPDDR (MT46H64M16) and Partial Array Selfrefresh on a K61 during power down.
But there's a problem with the memory mapping of the dram address space to row, bank and column:
The partial self refresh of LPDDR assumes bank as most significant adress-lines, then row and least column.
So if I want to refresh half of the memory array the first two of four banks are refreshed, quarter refreshes first bank, eighth refreshes first bank with MSB of row address 0 and so on.
But the Kinetis DRAM-controller maps the bank addresses between rows and columns (see Figure 34-68 of K61 RM) which means there will be no contiguous refreshed memory space when using Partial Array Selfrefresh.
In our application (with 16th PASR) we have 2048byte refreshed, then 30720bytes not refreshed, then again 2048bytes refreshed and so on, which is not usable.
What I'm now looking for is a possibility to disable this "bank interleaving" to have the banks mapped contignuous to the dram memory space.
I don't think there's a documented solution (as far as I can't find one), but perhaps there's an undocumented bit in the huge amount of unused dram configuration registers that maps the bank adress lines to the MSB of the dram adress space.
Thank you in advance for your help.