Al Ciplickas

S12XD document for EEprom programming (S12EETX4KV0)

Discussion created by Al Ciplickas on Oct 17, 2007
Latest reply on Oct 17, 2007 by Al Ciplickas
This may be obvious to some of you, but I can't understand the timing setting of the second example on page 25, using Figure 4-1. The osc. clk is 16 MHz and the Bus clk is 40 Mhz (Tbus=0.025 usec). I get EDIV[5:0]=10 and they get EDIV[5:0]=50. And if I used an osc. clk of 15 MHz, I would get and EDIV[5:0]=5. Where am I going wrong?