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Clarification on I2C SCL generation when bus busy condition in MPC8548

Question asked by Kasinathan Mareeswaran on Feb 25, 2015
Latest reply on Mar 3, 2015 by Serguei Podiatchev



I am working in MPC8548 PQ3 processor.

I am facing a issue that I2C bus is busy by keeping SDA as low from slave device. This problem happened due to reset happened in I2C master(i.e., MPC8548 resets) while doing some I2C transaction with I2C slave device. I hope that slave device didn't complete the transaction. And when I2C master came up from rest, it found that bus is busy considering slave is tying to send data '0' in SDA (could be valid data).


When I am referring MPC8548 Reference Manual, I found below piece of steps to do when bus is busy by keeping SDA as low

1. Disable the I2C module and set the master bit by setting I2CCR to 0x20

2. Enable the I2C module by setting I2CCR to 0xA0

3. Read the I2CDR

4. Return the I2C module to slave mode by setting I2CCR to 0x80



1. Will the above mentioned steps generate 1 clock cycle or 9 clock cycle?


As per I2C Specification, in this kind of scenario we need to generate 9 clock cycle for slave to finish its unfinished transaction

2. If this is the case, Do I need to execute the above mentioned step in a loop of 9 times?


It will be helpful if anyone answer for my queries?


Thanks and Regards,