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Is there a reason SDCKE 0 is paired with CLK1 rather than CLK0?

Question asked by Katrina Gundal-Zaidi on Feb 24, 2015
Latest reply on Feb 24, 2015 by Yuri Muhin

Looking at the multiple reference designs including the sabre board (dual-lite), the DRAM appears to be using the CLK1 clock pair with SDCKE0. Is there a reason SDCKE 0 is paired with CLK1 rather than CLK0?

 

We were unable to find an explanation in the chip documentation so if you could provide further info it would be greatly appreciated. We are trying to close out a design review...

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