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Powering down PLL for T4240 SD3

Question asked by eric skullerud on Feb 24, 2015

From study of Chapter 18 in the T4240 QorIQ Integrated Multicore Communications Processor Family Reference Manual, we think the correct address offset to read and write the bit fields in SERDES_x_PLLnCR0 is 0xFE000000 + 0xEC000 + 0x04 .

 

However, when we read and then write a change to this register, the expected behavior does not occur.

 

For example, if we toggle the state of bit 0 in that reg (the POFF bit), and then monitor the reference clock at the PCIe connector, we do not see any change, and in fact, we do not see any clock for either setting (POFF=0 or 1).

 

 

Similarly, to read the RCW (DCFG_CCSR_RCWSRn), the address we arrived at from Ch 27 is,

   FE000000 + E0000 + 0x100 + (4d x  I),  I = 0d to 15d.

 

However, the resulting register reads return values that don't match what uboot report for the RCW.

 

 

 

Can you please clarify if the above address interpretations are correct, and if not, what it should be?

 

 

Thank you.

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