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About HSYNC timing of CSI input in i.MX6DQ.

Question asked by Keita Nagashima on Feb 23, 2015
Latest reply on Mar 4, 2015 by Keita Nagashima

Dear Sir or Madam,



My customer will use the camera input format with "YCbCr 16bits 1cycle [Y(8bits)+CbCr(8bits)] + HSYNC/VSYNC + DE”

I got the attached information from TIC (SR# 1-1147203261).

Refer to page.3 in attached file.

HSYNC becomes Active(High) only in the Active Line and, HSYNC seems to become Low during the blanking.

Is it necessary to make HSYNC Low during blanking?


Best Regards,