We're developing with a NetBurner MOD54417, using the CS5 chip select and the FlexBus in 8 bit (no burst) mode. The peripheral
will be FTDI's FT232H USB chip in asynchronous FIFO mode. I'm new to the ColdFire, but I think I have it set properly for the bus
mode we want. However, CS5 is asserting twice during a byte write - once in the address setup cycle and once for the data. The
FlexBus specs show it as a single assertion. I'm thinking I must be missing something outside of the usual csar, csmr, and cscr
register setup. I realize I'll have to manipulate the timing a bit with a latch or counter to get the FT232H timing right, but I don't want
to deal with a doubled up chip select assertion as part of that.
NetBurner doesn't meddle with the CS5 signal from the ColdFire, they only have an address latch on board to de-multiplex the bus.
Register values for CS5:
csar = 0x04000000
cscr = 0x1140; //no CS5 delay, 4 waits (38 ns. CS assertion width)
csmr = 0x00000001
Attached is the logic analyzer trace. Cursor D is just to the right of the data becoming valid.
Any feedback on this issue will be greatly appreciated!