I am trying to use the Display Content Integrity Checker on the i.MX6Q running an RTOS. Sabrelite Rev D, display connected to the HDMI port.
So far I have set the registers manually to enable DCIC1 (the first one), and set the first region of interest top left co-ords (0,0), bottom left at (400, 400).
Bits in IOMUX_GPR10 [1:0] are set to 11b to route the HDMI signals back into DCIC1. When I did this, a checksum value appeared in DCIC1_DCICRCS (at 0x020E401C).
However: when the contents of the display change within the top left 400x400 pixel area on the screen, the checksum doesn't change. I'm checking the register at the command line every few seconds, with the display contents in the ROI different every time.
I only have one DCIC enabled, which only has one ROI enabled.
I changed the ROI to be the full 1024x768 dimensions of the display, with an animation running on screen.
I've tried setting the status bits to clear the interrupts in DCIC1_DCICS (bit 0 is correctly getting set because my reference checksum value of 0x0 doesn't match).
I've tried disabling the ROI (The calculated checksum clears to 0x0 when disabled), clearing the status bits, and re-enabling the ROI.
Still the checksum is the same value.
The only way the checksum value changes, is if I disable the HDMI output momentarily (By killing the display driver) and re-enable it again. Then a new CRC value appears in DCIC1_DCICRCS.
The behaviour I expected from the DCIC is that, when the actual display contents within the ROI changes, on the display, and therefore in the HDMI signal, the calculated CRC changes, every frame (60Fps).