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How to clear SPI transmit register

Question asked by Michael Schwager on Feb 17, 2015
Latest reply on Feb 20, 2015 by Michael Schwager

K60, MQX 4.1.

 

I’m writing a low-profile, lightweight SPI slave driver which I hope to eventually hook up to DMA.

At this point I’ve got roughly the same functionality as the Processor Expert driver, but I’m facing the same issue I had which initiated me wanting to write my own driver.

The SPI peripheral has a FIFO and a shift register.  The FIFO can be 4 deep, or 1 deep, but in any case, there is a FIFO and a shift register.

For transmit, once you write a value to the FIFO, it is immediately copied to the shift register, and as far as I know there is no way to clear the shift register other than to shift out the data with a master-initiated transaction.

But that’s exactly what I need to do to enable re-trying an aborted SPI transaction.  Flushing the FIFO with the appropriate bit (MCR->CLR_TXF) works fine to clear the FIFO, but it doesn’t clear out the previous value in the shift register.

 

I’ve tried disabling/enabling and halting/unhalting the thing, and I’ve also tried disabling the SCGC clock to the entire peripheral, but other than actually shifting out the bits with the master, I’m at a loss as to how to clear the shift register.

 

Any clues?

 

If there is no way to do this then I’ll put an extra step in the master to do a 1-byte transaction to clear it out when it knows it’s doing a retry.

 

Thanks

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