We have a question about i.MX6SDL eCSPI.
Would you let me know the pad state of MISO when SS signal is negated and i.MX6SDL is slave mode?
High impedance? or keep last output level?
Hello Satoshi Shimoda,
The i.MX6 ECSPI module has tri-state capabilities so the MISO gets to high impedance when the SS signal is negated while on Slave mode.
On my iMX6ULL evk, running ESCPI1 in slave mode, I see data on MISO when SS is asserted but it's not going high impedance when negated (it's conflicting with another slave's output). Is there a pin setting that I'm missing?
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