AnsweredAssumed Answered

i.MX6SDL MISO signal level when i.MX is slave and SS is negated.

Question asked by Satoshi Shimoda on Feb 17, 2015
Latest reply on Dec 7, 2017 by chris_f

Hi community,


We have a question about i.MX6SDL eCSPI.

Would you let me know the pad state of MISO when SS signal is negated and i.MX6SDL is slave mode?

High impedance? or keep last output level?



Best Regards,

Satoshi Shimoda