I need use 5 CSs to configure CS0(64MB), CS1(32MB), CS2(32MB), CS3(32MB), CS4(32MB) in i.MX502 based system.
In the IMX50RM the page 150, it says,
Off Chip Memories
The supported configurations are
• CS0(128M), CS1 (0M), CS2 (0M),CS3(0M)
• CS0(64M), CS1(64M), CS2(0M), CS3(0M)
• CS0(64M), CS1(32M), CS2(32M),CS3(0M)
• CS0(32M), CS1(32M), CS2(32M),CS3(32M)
However in the latter page, in the "23.2 Featrus".
• Up to four chip selects for external devices
• Flexible address decoding. Each chip select memory space determined separately, according to VIA port configuration (see Chip Select Memory Map).
Configurable Chip Select 0 base address (by VIA)
• Individual select signal for each one of the memory space defined. Up to 6 memory spaces may be defined and programmed individually.
• 128-bit external address bus, max memory size can be 256MByte (2 Gigabit).
Seems like max 6 memory spaces with 256MB might be possible.
Is it really possible?