AnsweredAssumed Answered

IMX6SL: does 8bit DDR eMMC interface work on this CPU?

Question asked by RobHawksFan on Feb 12, 2015
Latest reply on Feb 26, 2015 by RobHawksFan

I have an IMX6SL board that is based on the EVK design. Only, it boots from a Samsung eMMC v4.41 which seems to be working in SDR mode at 26Mhz.

 

> cat /sys/kenel/debug/mmc0

clock: 52000000 Hz

vdd: 7 (1.65 - 1.95 V)

chip select: 0 don't care

power mode: 2 (on)

bus width: 3 (8 bits)

timing spec: 5 (mmc high-speed 50Mhz)

 

I can't seem to get DDR mode to work when accessing the eMMC. I am using the BSP that was provided by FSL, the recent release with linux kernel 3.0.5.101 and FSL patches.

 

Under Linux the measured eMMC clock rate is ~26Mhz but what is reported above as part of the mmc0 kernel debug info is 52Mhz which is not the actual clock rate. It is reporting one rate but sending another.

 

The other strange thing was the measured eMMC clock under u-boot was 52Mhz vs 26Mhz under linux. I think the clock is correct under u-boot but it is still only using SDR mode. Anyone resolved any eMMC related issues for a similar platform?

 

When I try to force the DDR bit in the CPU all hell breaks loose and I can't talk to the eMMC.

Outcomes