SPI and DMA CS does not disable

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SPI and DMA CS does not disable

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pietrodicastri
Senior Contributor II

Good morning..

I am testing on the FRDM-K64.

I have initialized the SPI and DMA to transfer. The transfer is looking ok on the scope with one problem.

The second CS signal remain in the enable status in the end of the transfer, I would like to see it disabled as the other.

Suggestions???

Thank you

Pietro

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adriancano
NXP Employee
NXP Employee

Hi,

I apologize for the late response, I am not aware of an issue like this. But I have some points to check.

It is probably that your configuration has the continuous mode enable in the last transmission and this is causing the PCSx line remains low waiting for the next frame. Please check the status your are configuring for the PUSHR[CONT] bit in the last transfer.

Also, you need to ensure that in the last transfer the PUSHR[EOQ] bit is set to indicate is the last one in the queue and the bus becomes free.

Hope this information can help you

Best Regards,
Adrian Sanchez Cano
Technical Support Engineer
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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adriancano
NXP Employee
NXP Employee

Hi,

I do not completely understand what do you mean with the second CS? Can you please be more specific?

You can refer to this document, it might be useful for your application:

Using the DMA module in Kinetis Devices


Hope this information can help you

Best Regards,
Adrian Sanchez Cano
Technical Support Engineer
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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pietrodicastri
Senior Contributor II

Hello Adrian

Thank You for the assistance.

The signal I mean are the SPI0_PCS1 and SPI0_PCS0.

Everything is working with the surprise that the last transfer updates all of the PCSx signal as requested

only when the transfer begins, not when the transfer ends. The enabled PCSx in the last transfer remain enabled

when the transfer stops.

The trick is to add a dummy transfer with all of the PCSx signal disabled, but I don t like to do. I suppose a solution exists.

Thank You

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628 Views
adriancano
NXP Employee
NXP Employee

Hi,

I apologize for the late response, I am not aware of an issue like this. But I have some points to check.

It is probably that your configuration has the continuous mode enable in the last transmission and this is causing the PCSx line remains low waiting for the next frame. Please check the status your are configuring for the PUSHR[CONT] bit in the last transfer.

Also, you need to ensure that in the last transfer the PUSHR[EOQ] bit is set to indicate is the last one in the queue and the bus becomes free.

Hope this information can help you

Best Regards,
Adrian Sanchez Cano
Technical Support Engineer
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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627 Views
pietrodicastri
Senior Contributor II

Yes...

That's it

Thank You

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