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Could you tell me more about the WL3_WL0 of sect 61.9.8 SSI Transmit Clock Control Register .

Question asked by Takashi Takahashi on Feb 10, 2015
Latest reply on Feb 10, 2015 by igorpadykov

Dear community.

 

Could you tell me more suggestion about the WL3_WL0 of IMX6 RM  sect 61.9.8 SSI Transmit Clock Control Register (SSIx_STCCR) "? (What to do set?)

I got answers yesterday below from community  of Specifications of the I2S of RX of IMX6DL.

 

" One can do that is software skipping in used bits. Hardware

does not allow skip some bits, it send/receive all bits set by "WL" - Number of Bits/Word."

 

I do not anything has been set of WL3_WL0 register., but  play sounds correctly working.

Transfer the 16bit worth of data to 24bit register is operating normally.

 

If this setting is not something glitches etc will be assumed?

And ,What is the treatment the BSP entered 24-bit data lower 8-bit data  ?

 

 

 

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