i am using K60 tower board and using external clock 50 Mhz .i set PLL external clock as 100 Mhz(core)(core 100,bus 50Mhz,flash 25).
i noticed that reference clock divider 4,and(50/4=12.5),multiplication factor is 16.That means (12.5*16=200).Actually it is double of actual clock value.i dont understand is there any divide by factor?,
MCG_C5 = MCG_C5_PRDIV0(0x03);
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG_C6 = MCG_C6_VDIV0(0x00);
and another question is FLL clock reference divider is 1024 that means (50 Mhz/1024=48.828 Khz, ( MCG_C1_FRDIV(0x05) )
actually The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz.
But actual value grater than this.so there is any problem? .another question is how to disable PLL1 or PLL0 any one in use.
so please tell me