K60 Tower board clock settings

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K60 Tower board clock settings

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lijofrancis
Contributor III

hello sir,

i am using K60 tower board and using external clock 50 Mhz .i set PLL external clock as 100 Mhz(core)(core 100,bus 50Mhz,flash 25).

i noticed that reference clock divider 4,and(50/4=12.5),multiplication factor is 16.That means (12.5*16=200).Actually it is double of actual clock value.i dont understand is there any divide by factor?,

  MCG_C5 = MCG_C5_PRDIV0(0x03);

  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */

  MCG_C6 = MCG_C6_VDIV0(0x00);

and another question is FLL clock reference divider is 1024 that means (50 Mhz/1024=48.828 Khz,  ( MCG_C1_FRDIV(0x05) )

actually The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz.

But actual value grater than this.so there is any problem? .another question is how to disable PLL1 or PLL0 any one in use.


so please tell me


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mjbcswitzerland
Specialist V

Hi Lijo

Are you using a TWR-K60N512, K60D100M or K60F120M board?

In the K60F120 the VCO has a divide by two after it so a 200MHz VCO gives 100MHz clock - if you have one of the other boards the K60 on them has a different PLL and doesn't have the double-VCO output frequency; make sure that you have selected the correct board.

If not using the FLL (which is the case when the PLL is used) the FLL input is not important although it may still be good practice to set a suitable divider for it.

The PLLs are disabled by default and so if you don't use one of them there is nothig needed for it.

Regards

Mark

Kinetis: http://www.utasker.com/kinetis.html

K60: µTasker Kinetis TWR-K60N512 support / µTasker Kinetis TWR-K60D100M support / µTasker Kinetis TWR-K60F120M support

For the complete "out-of-the-box" Kinetis experience and faster time to market

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mjbcswitzerland
Specialist V

Hi Lijo

Are you using a TWR-K60N512, K60D100M or K60F120M board?

In the K60F120 the VCO has a divide by two after it so a 200MHz VCO gives 100MHz clock - if you have one of the other boards the K60 on them has a different PLL and doesn't have the double-VCO output frequency; make sure that you have selected the correct board.

If not using the FLL (which is the case when the PLL is used) the FLL input is not important although it may still be good practice to set a suitable divider for it.

The PLLs are disabled by default and so if you don't use one of them there is nothig needed for it.

Regards

Mark

Kinetis: http://www.utasker.com/kinetis.html

K60: µTasker Kinetis TWR-K60N512 support / µTasker Kinetis TWR-K60D100M support / µTasker Kinetis TWR-K60F120M support

For the complete "out-of-the-box" Kinetis experience and faster time to market

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lijofrancis
Contributor III

sir something to add on previous reply

i am using K60F120M Tower board for training actually i write code for it.when our pcb ready i change for to MK60FX512VLQ12.so please tell me any useful information for me

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mjbcswitzerland
Specialist V

Hi Lijo

When working with a 50MHz external oscillator the FLL is not used because its input frequency is not suitable. Also, there is no alternative when working with Ethernet since the clock must be synchronised with the PHY.

Therefore if you wanted to use the FLL instead you would need to use a different oscillator or crystal and also not use Ethernet.

Since the PLL is more flexibly and more stable than FLL there is little use for the FLL in Ethernet/USB designs with the K60.

Regards

Mark

Kinetis: http://www.utasker.com/kinetis.html

K60: µTasker Kinetis TWR-K60N512 support / µTasker Kinetis TWR-K60D100M support / µTasker Kinetis TWR-K60F120M support

For the complete "out-of-the-box" Kinetis experience and faster time to market

468 Views
lijofrancis
Contributor III

hai sir,

My eval board is K60F120M Tower board .But actually i am using for project the controller MK60FX512VLQ12

So is there any other setting difference other than Flash memory?,

sir , in your reply i realized that  the multiplier and divider is correct for MK60FX512,there is no doubling for it is it ?


and FLL clock reference divider is 1024 is the maximum divider is provided .so if am using FLL how can give correct division factor for this?

Thank you for your response

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